The present invention relates to the field of interconnect design and fabrication for semiconductor electronics.
Citation or identification of any reference in this Section or any section of this application shall not be construed that such reference is available as prior art to the present invention.
Heterojunction bipolar transistors (xe2x80x9cHBTxe2x80x9ds) fabricated on GaAs substrates using AlGaAs or InGaP emitters are suitable for efficient microwave power amplification. The high power generation requires the use of multiple emitter fingers spread over a large surface area to provide adequate thermal management (adequate heat dissipation and thermal uniformity) of the device.
For proper operation of the transistor, all parts of the device must be connected together so that the resulting power device exhibits uniform electrical and thermal characteristics. Because of the poor thermal conductance of the GaAs substrate, the ideal thermal and electrical designs often have contradictory requirements. For instance, better thermal designs require the emitter fingers to be spread apart, whereas better electrical designs require the same emitter fingers to be closely spaced. In practical device designs, several emitter fingers are co-located in a sub-cell, and multiple sub-cells are then re-connected within the device. The connection of emitter fingers within the sub-cell with low thermal resistance and low electrical resistance metals provide substantial stability against thermal runaway.
FIG. 1 shows a side cut view of a conventional GaAs-based HBT. An interconnect 120 provides electrical and thermal communication between each of the emitter fingers 102 in the HBT 100. Base fingers 104 are electrically insulated from the interconnect 120 by spacers 110. The spacers 110 prevent the interconnect 120 from creating an electrical short between the base fingers 104 and the emitter fingers 102. The spacers 110 may be any dielectric material such as silicon nitride, silicon dioxide or polyimide. Although the spacers 110 provide the necessary electrical insulation between the emitter fingers 102 and base fingers 104, the spacers also create undesirable electrical parasitic capacitance between the emitter and the base terminals in the HBT 100. This parasitic capacitance lowers the input impedance of the HBT and adversely impacts the microwave gain characteristics thereby degrading the high frequency performance of the HBT.
The fabrication of the interconnect 120, generally referred to as metallization, may be accomplished by sputtering, evaporation, or electroplating. The metallization process usually creates residual stress in the interconnect 120 that appears as an interfacial stress 150 acting on the emitter fingers 102. The interfacial stress may result in delamination of the emitter finger 102 from the interconnect 120 or from the underlying substrate 106 leading to a failure of the HBT. Even if the interfacial stress is not sufficient to cause delamination, the persistent interfacial stress degrades the long term reliability of the HBT. For instance, without intending to be bound by any theory, it is believed that the persistent interfacial stress enhances the creation of lattice defects during the normal operation of the device. Defects in HBTs at the interface or in the base layer may act as recombination centers thereby reducing the current gain. Further, such recombinations may release energy into the crystal lattice, which if under stress, may tend to create additional defects. This is a long term degradation mechanism for GaAs-based HBTs.
U.S. Pat. No. 5,734,193 issued to Bayraktaroglu, et al. on Mar. 31, 1998 (xe2x80x9cBayraktarogluxe2x80x9d) discloses the use of an air bridge to electrically insulate the emitter fingers from the base fingers while reducing the parasitic emitter-base capacitance by using air as the low dielectric spacer material. Bayraktaroglu, however, does not teach creating a low residual stress electrical contact.
U.S. Pat. No. 5,318,687 issued to Estes et al. on Jun. 7, 1994 (xe2x80x9cEstesxe2x80x9d) discloses a process of electrodepositing thin (between 0.6-0.7 xcexcm) gold X-ray lithography masks having low residual stress by using a plating bath containing between 8 to about 30 mg of arsenite per liter. Estes discloses using a 1.7 xcexcm thick polyimide as the plating base upon which the gold is directly deposited. Estes also discloses the use of 2.5 xcexcm thick heavily doped silicon as an alternative plating base along with other materials such as silicon nitride, silicon carbide, boron nitride, boron carbide, carbon (diamond), or other polymers. Estes does not, however, disclose depositing gold directly onto GaAs. Estes does not teach the problem of reducing parasitic capacitance while providing good thermal control of emitter fingers in GaAs-based HBTs.
Therefore, there remains a need for an interconnect for improved GaAs-based HBTs that provides for (a) adequate heat dissipation, (b) uniform emitter temperatures, and (c) low parasitic emitter-base capacitance.
In one embodiment, an interconnect for a heterojunction bipolar transistor having interdigitated emitter and base fingers is disclosed wherein the interconnect is essentially comprised of gold having a thickness greater than 1 micrometers, the interconnect in thermal and electrical contact with at least two of the emitter fingers and forming a bridge over each of the base fingers thereby maintaining electrical insulation between the base and emitter with a low emitter-base capacitance, wherein the interconnect is electrodeposited such that residual stress in the interconnect is low, wherein the bridge is an air bridge.
In another embodiment, an interconnect for a heterojunction bipolar transistor having at least two emitter fingers, the interconnect in thermal and electrical contact with at least two emitter fingers, is disclosed wherein the interconnect is electrodeposited to a thickness greater than 1 micrometers. A second interconnect may be thermal and electrical contact with each of the emitter fingers and a lead pad.
In another embodiment, a method of manufacturing an HBT interconnect is disclosed comprising the steps of: providing an HBT comprising an intrinsic device, a base ledge, and a dielectric passivation layer between an emitter contact and a base contact; establishing a post resist pattern characterized by a post resist thickness; depositing a seed metal over the post resist pattern; depositing a thick photoresist covering a portion of the seed metal, an uncovered portion of the seed metal defining a bridge area; plating gold on the uncovered portion of the seed metal forming the interconnect.